1. Field of the Invention
The present invention relates to phase frequency detectors (PFDs), and more particularly, to a system and method of detecting the absence (or failure) of a clock in a PFD and holding at least one output and/or device in a reset (or default) state until an active clock is detected.
2. Description of Related Art
Many electronic systems use internal clocks that are required to be phase-aligned to and/or frequency multiples of some external reference clock. For example, a central processing unit (CPU) might have an internal 2.4 GHz clock that is phase aligned to a bus clock running at 100 MHz. The frequency multiplication is important because multiplying frequencies on a circuit is much easier than transmitting 2.4 GHz clocks on a circuit board (or motherboard). The phase alignment is important so that data can be exchanged reliably between circuits in the 2.4 GHz core domain and the 100 MHz bus clock domain.
Typically, the reference clock enters a circuit and drives a phase locked loop (PLL), which then drives the system's clock distribution. PLLs generally include a phase frequency detector (PFD), a charge pump, a low pass filter, a bias generator, a voltage-controlled oscillator (or oscillation circuit), and an output converter. The function of the PFD is to compare the distributed clock to the incoming reference clock, and vary its output until the reference and feedback clocks are phase and frequency matched.
A commonly used PFD is the type 4 PFD, which includes two D flip-flops (e.g., a first and second flip-flop) and a NAND gate. A reference clock is provided to the first flip-flop and a feedback clock, which is traditionally provided by the oscillation circuit, is provided to the second flip-flop. The outputs of the flip-flops (e.g., an UP output and a DOWN output) are provided to the oscillation circuit and used to adjust the feedback clock until the reference and feedback clocks are phase and frequency matched. The feedback and reference clocks are considered to be matched when the widths of the pulses in the UP and DOWN outputs are matched.
A drawback with the type 4 PFD is the time required to recover from an inactive or changed reference clock. For example, when the reference clock is turned off, the UP output goes to zero and the DOWN output becomes a flat non-zero DC voltage. When the reference clock is turned back on, the DOWN output (due to its flat non-zero DC voltage state) will most likely have a pulse width that is much larger than the pulse width of the UP output. The outputs will then need to be adjusted until their pulse widths match, which can be a time consuming process.
Accordingly, it would be very desirable to provide a PFD that minimizes or eliminates the pulse width differential between the UP and DOWN outputs in response to a disturbance in at least one clock.